(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for the mounting of multiple semiconductor devices in one semiconductor device package.
(2) Description of the Prior Art
Continued progress in the semiconductor industry is achieved by continuous reduction in semiconductor device dimensions, this reduction in semiconductor device geometry must be achieved at a cost for the manufacturing of semiconductor devices that remains competitive. Interactive and mutually supporting technologies are used for this purpose, in many of the applications the resulting device density is further accommodated and supported by mounting multiple devices in one package.
In the field of high density interconnect technology, it is therefore frequently necessary to fabricate a multilayer structure on a substrate to connects integrated circuits to one another. To achieve a high wiring and packing density, many integrated circuit chips are physically and electrically connected to a single substrate commonly referred to as a Multi-Chip-Module (MCM). Typically, layers of a dielectric such as a polyimide separate metal power and ground planes in the substrate. Embedded in other dielectric layers are metal conductor lines with vias (holes) providing electrical connections between signal lines or to the metal power and ground planes. Adjacent layers are ordinarily formed so that the primary signal propagation directions are orthogonal to each other. Since the conductor features are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography, it is important to produce patterned layers that are substantially flat and smooth (i.e. planar) to serve as the base for the next layer.
Surface mounted, high pin count integrated circuit packages have in the past been configured using Quad Flat Packages (QFP's) with various pin configurations. These packages have closely spaced leads for making electrical connections that are distributed along the four edges of the flat package. These packages have become limited by having input/output (I/O) points of interconnect that are confined to the edges of the flat package even though the pin to pin spacing is small. To address this limitation, a new package, a Ball Grid Array (BGA) has been developed which is not confined in this manner because the electrical contact points are distributed over the entire bottom surface of the package. More contact points can thus be located with greater spacing between the contact points than with the QFP's. These contacts are solder balls that facilitate flow soldering of the package onto a printed circuit board.
Developments of increased device density have resulted in placing increased demands on the methods and techniques that are used to access the devices, also referred to as input/output (I/O) capabilities of the device. This has led to new methods of packaging semiconductor devices, whereby structures such as Ball Grid Array (BGA) devices and Column Grid Array (CGA) devices have been developed. A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier. The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mil spacings in regular and staggered array patterns. Due to the increased device miniaturization, the impact that device interconnects have on device performance and device cost has also become a larger factor in package development. Device interconnects, due to their increase in length in order to package complex devices and connect these devices to surrounding circuitry, tend to have an increasingly negative impact on the package performance. For longer and more robust metal interconnects, the parasitic capacitance and resistance of the metal interconnection increase, significantly degrading chip performance. Of particular concern in this respect is the voltage drop along power and ground buses and the RC delay that is introduced in the critical signal paths. In many cases the requirements that are placed on metal interconnects result in conflicting performance impacts. For instance, attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires. It is therefore the trend in the industry to look for and apply metals for the interconnects that have low electrical resistance, such as copper, while at the same time using materials that have low dielectric constants for insulation between interconnecting lines.
One of the more recent developments that is aimed at increasing the Input-Output (I/O) capabilities of semiconductor devices is the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on A1 pads on a semiconductor device, the bumps are interconnected directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path. This technology can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging, in which the packages are larger while more sophisticated substrates can be used that accommodate several chips to form larger functional units.
The flip-chip technique, using an area interconnect array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Temperature Coefficient of Expansion (TCE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
In general, Chip-On-Board (COB) techniques are used to attach semiconductor die to a printed circuit board. These techniques include the technical disciplines of flip chip attachment, wirebonding, and tape automated bonding (TAB). Flip chip attachment consists of attaching a flip chip to a printed circuit board or to another substrate. A flip chip is a semiconductor chip that has a pattern or arrays of terminals that is spaced around an active surface of the flip chip that allows for face down mounting of the flip chip to a substrate.
Generally, the flip chip active surface has one of the following electrical connectors: BGA (wherein an array of minute solder balls is disposed on the surface of the flip chip that attaches to the substrate); Slightly Larger than Integrated Circuit Carrier (SLICC), which is similar to the BGA but has a smaller solder ball pitch and a smaller diameter than the BGA; a Pin Grid Array (PGA), wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board so that precise connection can be made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror image of the recesses on the printed circuit board. After insertion, soldering the pins in place generally bonds the flip chip.
Recent developments in the creation of semiconductor integrated devices have seen device features being reduced to the micron and sub-micron range. Continued emphasis on improved device performance requires increased device operating speed, which in turn requires that device dimensions are further reduced. This leads to an approach that is applied to Ultra Large Scale Integration (ULSI) devices, where multi-levels of metal interconnects are used to electrically interconnect the discrete semiconductor devices on the semiconductor chips. In more conventional approaches, the different levels of interconnect are separated by layers of insulating materials. The various adjacent levels of metal can be interconnected by creating via openings in the interposing insulating layers. Typically, an insulating layer is silicon dioxide. Increased reduction of device size coupled with increased device density requires further reduction in the spacing between the metal interconnect lines in order to accomplish effective interconnects of the integrated circuits. This however is accompanied with an increase in capacitive coupling between adjacent lines, an increase that has a negative impact on device performance and on device operating speed. A method must therefore be found whereby devices can be mounted in very close physical proximity to each other without increasing capacitive coupling while also reducing the RC induced time delay of the circuit. One typical approach is to search for insulating layers that have low dielectric constants, ideally the dielectric constant of a vacuum. Another approach is to use electrical conductors for the interconnect lines that have low electrical resistivity thereby reducing the RC time delay. Another approach is to direct the packaging of semiconductor devices in the direction of wafer-like packages. This approach offers the advantages of being able to use standard semiconductor processing equipment and processes while it can readily be adapted to accommodate die shrinkage and to wafer-level burn-in and testing.
Current practice of mounting multiple chips on the surface of one chip carrier has led to the highlighted approaches of Multiple Chip Module (MCM) and Multiple Chip Package (MCP) packaging. These methods of packaging however are expensive while a relatively large size package is typically the result of this method of packaging. A method that can negate these negative aspects of multiple chip packaging is therefore required, the invention provides such a method.
FIG. 12 shows a cross section of a prior art chip assembly in which the following elements are highlighted:                60, the basic structure of the package that typically is a Printer Circuit Board; one or more layers of conductive interconnect may have been provided in or on the surface of the PCB 60; contact pads (not shown) are provided on the surface of PCB 60        61, the Integrated Circuit die that is at the center of the package; it must be emphasized that more than one IC die can be mounted inside the package of FIG. 12 in a manner similar to the mounting of the one IC die that is shown in FIG. 12        62, a substrate interface that has been provided with metal traces on the surface thereof, one or more layers of interconnect metal (such as traces or lines, vias, contact plugs, not shown in FIG. 12) may be provided in or on the surface of the substrate 62; points of electrical contact (not shown) are provided on the surface of substrate 62; conducting vias (not shown) may have been provided through the substrate 62 that connect overlying contact balls 64 with bond pads that have been provided on the surface of PCB 60        63, the lowest array of metal contact balls that forms the interface between the package that is shown in cross section in FIG. 12, the package of FIG. 12 is interconnect to surrounding electrical components by means of contact balls 63        64, the upper array of metal contact balls that connect the IC die 61 to the contact pads that have been provided on the surface of the substrate 62        65, bond wires that provide further interconnects between the substrate 62 and bond pads that have been provided on the surface of the PCB 60, and        66, an encapsulating epoxy based molding.        
The disadvantages of the package that is shown in cross section in FIG. 12 is that the wire bonding 65 adds parasitic inductance to the interconnect network which degrades the high-frequency performance of the package. Further, the number of input/output interconnects that can be provided to the IC die 61 of the package of FIG. 12 is limited due to the pitch of the wire bond lines 65.
U.S. Pat. No. 5,811,351 (Kawakita et al.) shows a stacked chip structure with bumps on the overlying chip.
U.S. Pat. No. 5,522,435 (Takiar et al.) shows a stacked multi-chip module.
U.S. Pat. No. 5,994,166(Akram et al.) recites a stack chip package using flip chip contacts.
U.S. Pat. No. 5,952,725(Ball) shows a stacked chip device with solder ball connectors.
U.S. Pat. No. 5,608,262 (Degani et al.) show a method and package for packaging multi-chip modules without using wire bond interconnections.
Article, published as part of the 2000 Electronic Components and Technology conference of May 21, 2000 through May 24, 2000, author: Jean Dufresne, title: Assembly technology for Flip-Chip-on-Chip (FCOC) Using PBGA Laminate Assembly. Reference number: 0-7803-5908-9/00, IEEE.